1. Field of the Invention
This invention generally relates to a semiconductor device and a method for fabricating the same, and more particularly to an interconnect structure and a method for fabricating the same.
2. Description of Related Art
For current VLSI fabrication processes, most semiconductor devices use two or more interconnects for routing in order to achieve a higher integration level.
For a conventional process for multi-level interconnects, a silicon oxide inter level dielectric (ILD) is formed on the substrate to cover the device on the substrate. Then a contact window is formed in the ILD electrically connected to the selected device. A conducting line is formed on the ILD to electrically connect to the contact window. The conducting line is formed by stacking a Ti/TiN barrier layer, an Al layer, and a Ti/TiN barrier layer. The above process is for a single-level interconnect. The multi-level interconnects can be fabricated by repeating the above steps.
However, problem occurs while a contact window is formed in the second-level ILD on the first-level interconnect. Conventionally, the contact window is formed by forming an opening in ILD to expose the conducting line and then filling a conducting material into the opening. However, when etching the ILD to form the opening, over-etching may happen due to inappropriate etching control. If the etching process does not stop on the Ti/TiN barrier layer above the Al layer, the Al layer will be etched so that the resistance will increase. For a process with a line width of 0.12 μm or below, this etching process is more difficult to control. Hence, the issue of over-etching becomes more critical for a process with a line width of 0.12 μm or below.